A host integrated circuit such as a system-on-a-chip (SoC) is typically integrated with a plurality of peripheral devices that can each trigger an interrupt to the SoC's processor. To accommodate the interrupt processing, a general purpose input/output (GPIO) architecture may be used in which the SoC includes a unique GPIO pin for each peripheral device's interrupt signal. The SoC then determines immediately the identity of the interrupting peripheral through the identity of the corresponding GPIO pin. Although interrupt processing latency is thus reduced, direct GPIO embodiments suffer from the resulting increased pin count as the SoC must then have a dedicated GPIO pin for each peripheral device.
The SoC pin count may be reduced at the cost of increasing latency in a conventional open-drain embodiment for a host integrated circuit in which the interrupts from a plurality of peripheral devices are all aggregated onto a common pin to the SoC. The default state of the common pin is typically logic high such as through a weak pull-up device. Should a peripheral device want to trigger an interrupt through the common pin, the peripheral device overcomes the weak pull-up device to discharge the common pin voltage to ground. Although just a single common pin can thus service multiple peripherals in an open-drain implementation, the SoC must then poll the peripheral devices to determine which device originated the interrupt, which increases interrupt processing latency.
To reduce interrupt latency, a row-column matrix approach may be used in which the peripheral devices are arranged with regard to a matrix of row and column wires or signal leads. Each peripheral device couples to between a corresponding row and column lead. For example, a matrix of leads formed into three rows and three columns may couple to nine peripheral devices. A first peripheral device couples to the intersection of a first row and a first column, a second peripheral device couples to the intersection of the first row and a second column, and so on such that a ninth peripheral device couples to the intersection of a third row and a third column. Each row couples to a corresponding GPIO pin on the host device. Similarly, each column couples to a corresponding GPIO pin on the host device. In a matrix having m columns and n rows, the host device would thus need to devote the sum of (m+n) GPIO pins for coupling to the matrix. Although the number of necessary GPIO pins is reduced as compared to a direct GPIO architecture, row-column matrix architectures still consume a substantial number of GPIO pins. Moreover, only two peripheral devices may trigger an interrupt at any given time as additional interrupts from other peripheral devices cannot be uniquely identified in a row-column matrix approach. Finally, the processing of the row and column GPIO signals at the host device is complex and consumes substantial power.
Accordingly, there is a need in the art for digital input aggregation architectures that accommodate the processing of interrupts from multiple peripheral devices with reduced latency and also reduced pin count.